1. Technical Field
This invention relates to a process and apparatus for removing metal ions from wastewater. In one aspect, this invention relates to a process and apparatus for removing copper ions from wastewater from a chemical mechanical polishing (CMP) of integrated circuit microchips.
2. Background
Semiconductor microelectronic chip (microchip) manufacturing companies have developed advanced manufacturing processes to shrink electronic circuitry on a microchip to smaller dimensions. The smaller circuitry dimensions involve smaller individual minimum feature sizes or minimum line widths on a single microchip. The smaller minimum feature sizes or minimum line widths, typically at microscopic dimensions of about 0.2-0.5 micron, provide for the fitting of more computer logic onto the microchip.
An advanced new semiconductor manufacturing technology involves the use of copper in place of aluminum and tungsten to create a copper microchip circuitry on a silicon wafer. The copper has an electrical resistance lower than aluminum, thereby providing a microchip which can operate at much faster speeds. The copper is introduced to ULSI and CMOS silicon structures and is utilized as interconnect material for vias and trenches on these silicon structures.
ULSI silicon structures are Ultra Large Scale Integration integrated circuits containing more than 50,000 gates and more than 256K memory bits. CMOS silicon structures are Complimentary Metal Oxide Semiconductor integrated circuits containing N-MOS and P-MOS transistors on the same substrate.
For fully integrated multi-level integrated circuit microchips, up to 6 levels, copper now is the preferred interconnect material.
A chemical mechanical polishing (CMP) planarization of copper metal layers is used as a part of the advanced new semiconductor manufacturing technology. The chemical mechanical polishing (CMP) planarization produces a substrate working surface for the microchip. Current technology does not etch copper effectively, so the semiconductor fabrication facility tool employs a polishing step to prepare the silicon wafer surface.
Chemical mechanical polishing (CMP) of integrated circuits today involves a planarization of semiconductor microelectronic wafers. A local planarization of the microchip operates chemically and mechanically to smooth surfaces at a microscopic level up to about 10 microns (.mu.m). A global planarization of the microchip extends above about 10 microns (.mu.m) and higher. The chemical mechanical polishing planarization equipment is used to remove materials prior to a subsequent precision integrated circuit manufacturing step.
The chemical mechanical polishing (CMP) planarization process involves a polishing slurry composed of an oxidant, an abrasive, complexing agents, and other additives. The polishing slurry is used with a polishing pad to remove excess copper from the wafer. Silicon, copper, and various trace metals are removed from the silicon structure via a chemical/mechanical slurry. The chemical/mechanical slurry is introduced to the silicon wafer on a planarization table in conjunction with polishing pads. Oxidizing agents and etching solutions are introduced to control the removal of material. Deionized water rinses often are employed to remove debris from the wafer. Ultrapure water (UPW) from reverse osmosis (RO) and demineralized water also can be used in the semiconductor fabrication facility tool to rinse the silicon wafer.